The present invention relates to a manufacturing method of an LDD (lightly doped drain)-type MOS transistor, which method is intended to prevent the undesired phenomenon that impurity ions penetrate through a gate electrode to reach a channel region when they are introduced into source and drain regions.
Conventional methods of manufacturing semiconductor devices of the above type are associated with the problem that impurity ions pass through a gate electrode to reach a channel region when impurity ions are implanted into source and drain regions in such cases that the gate electrode is thin or made of polysilicon, or an acceleration voltage of the ion implantation is high.
In the case of a gate electrode made of polysilicon, since its crystal grains usually have a pillar-like structure, ions incidentally launched into a crystal grain boundary do not remain within the gate electrode but reach the channel region. As a result, the impurity concentration in the channel region is locally-reduced, to decrease the threshold voltage Vth.
Further, the conventional manufacturing methods encounter the following problem when the polysilicon gate electrode is employed that is heavily doped to provide n- or p-type conduction. If the source and drain regions are to be doped to provide a conduction type opposite to that of the gate electrode, impurity ions for the source and drain regions that are mixed into the gate electrode will increase the resistance of the gate electrode.
The present invention has been made to solve the above problems in the art, and has an object of providing a manufacturing method of the above type of semiconductor device, in which method, in implanting impurity ions into source and drain regions, their introduction into a channel region through a gate electrode can be avoided and the degree of their introduction into the gate electrode is reduced.
According to the invention, a manufacturing method of a field effect transistor comprises the steps of:
forming a gate electrode on a semiconductor substrate;
forming an insulating film only on a top surface or at least on the entire surface of the gate electrode; and
implanting impurity ions into source and drain regions from above the entire semiconductor substrate.
The above manufacturing method may further comprises the steps of:
forming vertical layers adjacent to side surfaces of the gate electrode;
forming a second insulating film at least on the top surface of the gate electrode; and
implanting second impurity ions into the source and drain regions from above the entire semiconductor substrate.
With the above manufacturing method, since impurity ions go through at least one amorphous layer, where they are scattered, the possibility that impurity ions penetrate through the crystal grain boundaries of the polysilicon gate electrode becomes extremely small. In the case of implanting ions to produce p-type source and drain regions in an n-type Si substrate in a BF2 atmosphere under the conditions of, for instance, E=70 keV and Q=5xc3x971015 cmxe2x88x922, an oxide film of 60 nm in thickness that is formed on the gate electrode can interrupt 50% of the ions because the projected range of the ions is about 60 nm.